SHARC+ Single Core High Performance DSP (Up to 1 GHz)ADSP-21562/21563/21565/21566/21567/21569

來源：ADI 時間：2024-09-14

SYSTEM FEATURES

Enhanced SHARC+ high performance floating-point coreUp to 1 GHz5 Mb (640 kB) Level 1 (L1) SRAM memory with parity(optional ability to configure as cache)32-bit, 40-bit, and 64-bitfloating-point support32-bit fixed pointByte, short word, word, long word addressed

Powerful DMA systemOn-chip memory protectionIntegrated safety features17 mm × 17 mm, 400-ball CSP_BGA (0.8 mm pitch), RoHScompliant120-lead LQFP_EP (0.4 mm pitch), RoHS compliantLow system power across automotive temperature range

MEMORY

Large on-chip Level 2 (L2) SRAM with ECC protection, up to8 Mb (1 MB)One Level 3 (L3) interface optimized for low system power,providing 16-bit interface to DDR3/DDR3L SDRAM devices

ADDITIONAL FEATURES

Security and ProtectionCrypto hardware acceleratorsFast secure boot with IP protectionEnhanced FIR and IIR accelerators running up to 1 GHzAEC-Q100 qualified for automotive applications

APPLICATIONS

Automotive: audio amplifier, head unit, ANC/RNC, rear seatentertainment, digital cockpit, ADAS

Consumer: speakers, sound bars, AVRs, conferencing systems, mixing consoles, microphone arrays, headphones

SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.

SHARC+ Single CoreHigh Performance DSP (Up to 1 GHz)

ADSP-21562/21563/21565/21566/21567/21569

Rev. D

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GENERAL DESCRIPTION

Reaching speeds of up to 1 GHz, the ADSP-2156x processorsare members of the SHARC® family of products. The ADSP-2156x processor is based on the SHARC+® single core. The

ADSP-2156x SHARC processors are members of the SIMDSHARC family of digital signal processors (DSPs) that featureAnalog Devices, Inc., Super Harvard Architecture. These 32-

bit/40-bit/64-bit floating-point processors are optimized forhigh performance audio/floating-point applications with largeon-chip static random-access memory (SRAM), multiple inter

nal buses that eliminate input/output (I/O) bottlenecks, andinnovative digital audio interfaces (DAI). New additions to theSHARC+ core include cache enhancements and branch predic

tion, while maintaining instruction set compatibility to previous

SHARC products.

By integrating a rich set of industry-leading system peripheralsand memory (see Table 1), the SHARC+ processor is the platform of choice for applications that require programmability

similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in oneintegrated package. These applications span a wide array of

markets, including automotive, professional audio, and industrial-based applications that require high floating-pointperformance.

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